See this..现在一个四个结的门电路大概要100NM乘100NM

来源: 于 2024-12-11 08:21:52 [博客] [旧帖] [给我悄悄话] 本文已被阅读：次

Density of logic transistors (solid line) has advanced on average by 2× per generation. Dotted line is estimated density from pitch scaling alone. SRAM transistor densities, derived from bit cell area, 4 assumes 6-transistors per cell. Transistor density data points were obtained by dividing reported total transistors by reported die area 12 per chip.